adding reset function to D Flip FLOP | Forum for Electronics
Current Mode Logic Divider
adding reset function to D Flip FLOP | Forum for Electronics
Figure 5.21 from Cmos Logic and Current Mode Logic 5.1 Introduction | Semantic Scholar
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Performance evaluation of the low-voltage CML D-latch topology - ScienceDirect
ECEN620: Network Theory Broadband Circuit Design Fall 2022
A Novel Ultra High-Speed Flip-Flop-Based Frequency Divider: Ravindran Mohanavelu and Payam Heydari | PDF
DFF-based CMOS clock divider. | Download Scientific Diagram
Help me calculate the device size of CML/SCL latch design and simulate the gain of it | Forum for Electronics
KR100682266B1 - Differential output tspc d-type flip flop and frequency divider using it - Google Patents
MIPI homepage CMOS prescaler basics
A Dynamic Current Mode D-Flipflop for High Speed Application | Semantic Scholar
Schematic of standard CML master-slave D-flip flop. | Download Scientific Diagram
An active inductor employed CML latch for high speed integrated circuits | SpringerLink
An improved current mode logic latch for high‐speed applications
Electronics | Free Full-Text | A Power Efficient Frequency Divider With 55 GHz Self-Oscillating Frequency in SiGe BiCMOS
Figure 1 from Design of low-power high-speed dual-modulus frequency divider with improved MOS current mode logic | Semantic Scholar
CML based DFF combined with NAND function used in 4/5 prescaler block | Download Scientific Diagram
Analysis and Design of High-Speed CMOS Frequency Dividers
Figure 4 from Low power inductor-less CML latch and frequency divider for full-rate 20 Gbps in 28-nm CMOS | Semantic Scholar
KR100969864B1 - Cml type d flip-flop and frequency divide-by-odd number using the same - Google Patents
4-bit Counter Using High-Speed Low-Voltage CML D-Flipflops | Semantic Scholar
Figure 1 from A 45 mW RTD/HBT MOBILE D-Flip Flop IC Operating up to 32 Gb/s | Semantic Scholar
CML based DFF used in 4/5 prescaler block | Download Scientific Diagram
Circuit configuration of the proposed NDR-based CML D flip-flop | Download Scientific Diagram
